AMD Unveils the Next Generation: Bulldozer, Bobcat and Hybrid Chips

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It’s been a long time since the last major AMD microarchitecture refresh, and in the meantime, Intel’s handily won the performance crown. The second-place chipmaker hasn’t spent its time idly, working instead on their first entirely-new x86 chips in close to a decade.

For AMD, Bulldozer and Bobcat are the future. Are they right?

As the name implies, the code-named “Bulldozer” cores are going to be AMD’s heavy lifters. Geared for performance, these chips will be mainstream and high-end desktop processors, as well as the Magny-Cours server replacement. Bulldozer is an entirely new way of constructing an x86 CPU.

Except for the very low-end of the notebook and desktop marketplace, computer CPUs today are at least dual-core.  That means, typically, that these systems have a single processor with two physically distinct processing cores, bound together on one piece of silicon. High-end servers might have up to twelve per CPU. They might share some L3 cache, but that’s it. It’s like having a single road with two one-bedroom houses on it – the road controls how many people can get to either house, but each house cares for its inhabitants separately.

Intel works to increase the performance of this design with enhancements such as HyperThreading.  HyperThreading creates two virtual, or logical, cores for every physical core. There are obvious performance benefits in some circumstances; additionally, it maximizes resource efficiency by minimizing the amount of time a core can sit around idle.

AMD is looking to take a different approach with a similar goal in mind.  Instead of joining two entirely discrete cores together on a single chip, it creates a heterogenous mix of architectures with some separate processing parts and other shared resources. To continue the house analogy further, Bulldozer replaces the two houses, each with its one habitant, with a two-bedroom residence. Some parts of the house, such as the front door, are shared, but each resident gets their own living space.

Module vs core
The diagram on the right showcases a theoretical Bulldozer processor module. Internally, AMD is calling these units “modules”, but they’ll appear to the operating system as discrete cores (a dual-core chip will have one module with two integer execution cores, a quad-core chip will have two modules with four cores, ad infinitum).

Until now, there have been two main approaches to multithreading within the confines of a single system. SMT (simultaneous multithreading), which is Intel’s HyperThreading approach, and CMP (chip-level multiprocessing), which is what AMD has relied upon up to this point. SMT counts on the fact that the chip’s cores will be underused, and CMP gives each thread its own core.

Bulldozer is a third approach. Each core has its distinctive processing circuitry, with its own integer scheduler, pipelines and L1 cache. These cores share the floating point architecture (stylized in the middle) as well as the L2 cache.

Basically, AMD is taking the bits of the chip architecture that are underutilized in traditional, non-SMT multicore processors and removing the redundancy. These resources are now shared between the two cores.

Now each thread gets its own core, and each core can take from the pool of shared resources. This is why a dual-module, quad-core system will, for example, appear as four cores in an application like Windows’ Task Manager.

More modules, more cores
To build a fully-fledged Bulldozer CPU, AMD will take multiple modules and stick them together on a single die along with a pool of shared L3 cache, an integrated memory controller and the integrated Northbridge. The memory controller being used in the new Bulldozer CPUs is new, too; implemented with an eye to virtualization enhancements, it’s the first significant redesign since 2007.

As mentioned, then, a CPU built with four modules will be marketed – and used – as an eight-core CPU. At this point in time, AMD is committing to three diffrerent BD (Bulldozer) processors: “Interlagos” and “Valencia”, which use 16 and 8 cores, respectively, are both aimed at replacements for the Magny-Cours-based Opteron line of server processors.  There’s also “Zambezi”, which is a high-end consumer desktop that will take the flagship title from AMD’s current Thuban-based Phenom II X6 six-core CPUs.

Higher performance, lower power
Compared to their current server chips, AMD is betting on a 50% increase in processor throughput with only 33% more cores, all in the same power envelope. To entice enterprise customers to make the upgrade, AMD has engineered the new BD chips to be backwards compatible with current server hardware; the new chips can literally become drop-in replacements for the previous generation.

Consumers, however, don’t get off so easily. Due to changes in power and architecture, Bulldozer almost certainly won’t be suitable for use as a similar drop-in replacement. Instead, AMD will likely create an AM3+ socket (over their current AM3; it’s similar to the AM2+ socket created when AM2 was current) for new chips – these CPUs can’t be used in anything but an AM3+ socket, but an AM3+ socket can use any AM3 CPU.

In addition to the more efficient use of the silicon itself, AMD’s new CPUs will be built on a 32nm manufacturing process by spin-off GlobalFoundaries. These will be AMD’s first 32nm offerings.

An extra note: while current AM3 CPUs support DDR2 memory, AM3+ CPUs will not.

Will AMD’s hybrid modular architecture be enough to satisfy customers’ ever-increasing demands? John Fruehe, AMD’s Director of Product Marketing for Server and Workstation Products, commented on the issue in a recent AMD blog post:

“But the key to an architecture like this is understanding how to push the limits, but not go too far. Sharing everything results in low power consumption, but terrible performance. Sharing nothing results in higher performance, but you get hammered by the power consumption and the cost of the die. So the key to a modular architecture will be how successfully you plan the shared components to maximize your design goals.”

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